• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
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    • 专利摘要:
    The processor includes a mapping engine and a moving engine that transparently reconfigures physical memory to achieve addition, removal or replacement of memory modules. The mapping engine registers store the FROM and TO physical addresses that enable the engine to virtualize the physical address of the memory module being reconfigured and provide real-time reconfiguration using hardware rather than software. Using the FROM and TO physical addresses to select the source and target, the mobile engine copies the contents of the memory module to be removed or reconfigured to the remaining or inserted memory module. The physical address associated with the reconstructed memory module is then reallocated to the memory module receiving the copied content, thereby virtualizing the physical from the addressable physical address space being used by the operating system to the virtual physical address space. Create a mapping. During the process of moving memory contents, the mapping engine maps write memory request addresses addressed to the real address space currently associated with the reconstructed memory module to the FROM and TO physical address spaces. As will be appreciated, memory modules can be inserted, removed or replaced in physical memory without the operating system directing and controlling the reconfiguration of the physical memory to achieve physical memory changes.
    公开号:KR20040032745A
    申请号:KR1020030062049
    申请日:2003-09-05
    公开日:2004-04-17
    发明作者:아리밀리라비쿠마；도드슨존스티븐；가이산지브；라이트케네스리
    申请人:인터내셔널 비지네스 머신즈 코포레이션；
    IPC主号:
    专利说明:

    METHOD AND SYSTEM OF MANAGING VIRTUALIZED PHYSICAL MEMORY IN A MULTI-PROCESSOR SYSTEM}
    [17] FIELD OF THE INVENTION The present invention relates to data processing, and more particularly to managing physical memory in data processing systems. More specifically, the present invention relates to a method and system for managing physical memory in a data processing system automatically from operating system control.
    [18] In computer systems, it is common that there is a one-to-one correspondence between the memory address generated by the processor and a particular area of the system's physical memory. This limits the operating system and applications to address space determined by the actual physical memory installed in the system. In addition, many modern computer systems execute multiple concurrent tasks or processes, each with its own address space. Since many processes use only a small portion of their address space at any given time, allocating a full complement of memory to each task and operating system is wasteful. Modern computer systems have overcome this limitation by using virtual memory, which implements a translation table that maps program addresses (or virtual addresses) to real memory addresses. Virtual memory allows a program to run on something that looks like large, contiguous physical memory allocated to the program. In practice, however, the physical memory available in the virtual memory system is shared between multiple programs or processes. The virtual address used in the process is translated into the physical address of physical memory by a combination of computer hardware and software. This process is called memory mapping or address translation.
    [19] In virtual memory systems, the allocation of memory is most often performed by operating system software (OS). It is a function of the operating system to ensure that the data and code the program is currently using are in main memory and that the translation table can correctly map virtual addresses to physical addresses. This requires an interrupt in the instruction sequence so that the normal program flow can allocate physical memory to the area where privileged kernel code is being accessed in order to continue without error. This interrupt and kernel processing to allocate physical memory requires a significant amount of processing time and messes up the usual pipelining of instructions through the CPU.
    [20] If physical memory is reconfigured while the computer system is operating, the load on the operating system managing the physical memory increases. If the physical memory size increases or decreases, or if a memory module is replaced during system operation (for example, a failure occurs in a memory module that requires replacement), the OS temporarily interrupts the task being processed. The system memory configuration information of the conversion table is modified, the data is stored from the bad memory device to the disk using the converted physical address, and the remaining memory device is reconfigured. When a memory device is removed, the OS invalidates the physical address space of the removed device, maintains the invalid address space so that the invalid address space cannot be used, and basically the addressable space of the memory system. leaves a block of space that is not available in space. The operating system then must map logical addresses to physical addresses to avoid pages with bad memory locations. These problems increase the load on the OS and complicate the control of memory. There is a need for a method and system for physical memory control that solves the above problems of the prior art and can dynamically reconfigure physical memory as required.
    [1] 1 is a data processing system implemented in accordance with a preferred embodiment of the present invention.
    [2] 2 is a block diagram representation of a memory address translation process for a memory system of the data processing system shown in FIG. 1, in accordance with a preferred embodiment of the present invention.
    [3] 3 is a simplified diagram of the data processing system shown in FIG. 1 for the case where a memory module is being removed from a physical memory system, in accordance with a preferred embodiment of the present invention.
    [4] 4 is a simplified diagram of the data processing system shown in FIG. 1 for the case where a memory module is being removed from a physical memory system, in accordance with a preferred embodiment of the present invention.
    [5] <Explanation of Signs of Major Parts of Drawings>
    [6] 10: processor unit
    [7] 12: interconnect
    [8] 14: processor core
    [9] 26: mapping engine
    [10] 28: moving engine
    [11] 24: memory controller
    [12] 204: Convert segment table
    [13] 206: virtual address space
    [14] 208: Convert page table
    [15] [Related Application]
    [16] The present application relates to the application "Method and System of Managing Virtualized Physical Memory in a Memory Controller and Processor System" (document AUS920020200US1) and the application "Method and System of Managing Virtualized Physical Memory in a Data Processing System" (document AUS920020202US1). Related application. The contents of these applications are incorporated herein by reference.
    [21] According to a preferred embodiment, a method and system are provided for managing virtualized physical memory of a multiprocessor system. The multiprocessor system is coupled to physical memory including a plurality of memory modules to store data as a plurality of memory blocks, each memory block comprising a contiguous byte of physical memory, wherein the multiprocessor system includes at least one Further connected to a memory controller of the memory controller, wherein each memory controller of the at least one memory controller includes one or more memory modules of the plurality of memory modules connected thereto, and each memory controller of the at least one memory controller is connected to it. Respond to memory access by writing and reading a memory block stored within one or more of the memory modules. The multiprocessor system includes a processor device for creating a memory access including a real address associated with a memory location of the physical memory for reading and writing data. A register in the processor device stores a first field that stores a FROM real address corresponding to a first memory module of the plurality of connected memory modules, and a TO real address corresponding to a second memory module of the plurality of connected memory modules. A second field, wherein the first memory controller coupled to the first memory module is programmed to respond to a memory request addressed to the FROM physical address, and the second memory controller coupled to the second memory module is configured to include the TO physical address. It is programmed to respond to memory requests addressed at. In response to a notification that configurations of the first memory module and the second memory module are being modified, the plurality of memory blocks are allocated from the first memory module to the second memory module based on the FROM real address and the TO real address. A moving engine in the processor device for copying is provided. A write memory request addressed to the actual address stored in one of the first field or the second field during a time period during which the mobile engine is copying the plurality of memory blocks from the first memory module to the second memory module; In response to the generating processor device, generating a write memory request addressed to the FROM real address and the TO real address, wherein the mobile engine copies the plurality of memory blocks from the first memory module to the second memory module; A mapping engine in the processor device is provided that reprograms the second memory controller to respond to a memory request addressed to the FROM real address after the time period in which it resides.
    [22] In another embodiment, the processor apparatus requesting a write memory address addressed to the FROM physical address during the time period during which the mobile engine is copying the plurality of memory blocks from the first memory module to the first memory module. In response, the mapping engine issues the write memory request addressed to the FROM real address and TO real address.
    [23] In another embodiment, after the time period during which the mobile engine is copying the plurality of memory blocks from the first memory module to the first memory module, the mapping engine causes the second memory controller to move to the FROM real address. The first memory module is removed from the physical memory system after enabling to respond to an addressed memory access.
    [24] In another embodiment, the FROM real address is current addressable of the physical memory system before the time interval during which the mobile engine is copying the plurality of memory blocks from the first memory module to the first memory module. In space.
    [25] In another embodiment, the second memory module is inserted into the physical memory system before the mobile engine copies the plurality of memory blocks from the first memory module to the second memory module.
    [26] In another embodiment, the FROM physical address is a current address of the physical memory system address before the time interval during which the mobile engine is copying the plurality of memory blocks from the first memory module to the first memory module. It is outside the available space.
    [27] <Example>
    [28] Referring to the drawings and in particular to FIG. 1, there is shown a high-dimensional block diagram of a multiprocessor (MP) data processing system that supports memory management of virtualized physical memory, in accordance with an embodiment of the present invention. As shown, the data processing system 8 includes multiple (eg, 64) processing units 10 connected for communication by a system interconnect 12. Each processing unit 10 is an integrated circuit that includes one or more processor cores 41. In addition to registers, instruction flow logic, and execution units used to execute program instructions, each processor core 14 may include instructions and operand data (accessible by the associated processor core 14). data level (16, 18) and associated Level One (L1) instructions that temporarily buffer the operand data, respectively.
    [29] As shown in FIG. 1, the memory hierarchy of the data processing system 8 also includes one or more memory modules (shown as memory modules M1, M2, and M3) that form the lowest level volatile data storage devices in the memory hierarchy. On-chip level two (L2) cache used to stage instruction and operator data from the physical memory 22 to the processor core 14 One or more lower levels of cache memory, such as (20). As will be appreciated by those skilled in the art, each successive lower level of the memory hierarchy can generally store more data than the higher level, but has a higher access delay. As shown, physical memory 22 interfaced to interconnect 12 by memory controllers 23, 34, and 44 may store operand data and portions of one or more operating systems and one or more application programs. Memory controllers 24, 34, and 44 are connected to and control corresponding memory modules M1, M2, and M3, respectively (although only shown as being connected to a single memory module, respectively, each memory controller is a plurality of memory systems 22). It should be noted that the memory module of the module can be controlled). A set comprising all or part of the memory modules M1, M2 and M3 constitutes a set of physical memory resources for the operating system and applications of the machine.
    [30] System interconnects 12, which may include one or more buses, switch fabrics, or other interconnect architectures, may include devices connected to system interconnects 12 (eg, processing unit 10, memory controllers). 23, 34 and 44, etc.) as a conduit for communication. A typical transaction of system interconnect 12 may include a transaction field that indicates the format of the transaction, one or more tags that indicate the source and / or the intended destination of the transaction, and a request that may include address and / or data. Starts from. Preferably, each device connected to the system interconnect 12 snoops all the transactions of the system interconnect 12 and responds to the request with a snoop response as appropriate. Such operations may include specifying a source of data on the system interconnect 12, storing data provided by the requesting snooper, invalidating the cached data, and the like. In addition, the input / output connector 52 is connected to the interconnection 12, and provides a conduit for communication between another device connected to the interconnection 12 and an external device connected to the PCI bus 58 through a bridge (58). to provide.
    [31] The data processing system 8 uses a virtual memory system, which implements a translation table that maps program addresses (or effective addresses) to real memory addresses. Virtual memory systems allow the available physical memory to be shared among multiple programs or processors. The processing unit 10 provides an address translation mechanism that translates the effective address (EA) into a physical address (PA) that points to the location of the actual physical memory, whereby the address space of the processing unit ("logical address space") is available. It may have a different size from the memory 22. Virtual memory systems also allow multiple programs to reside simultaneously in system memory without having to know the location of each physical base address. Rather, many such programs only need to know their logical base address. Also, instead of attempting to maintain translations or mappings for each possible valid address, the virtual memory system partitions the valid physical memory into blocks. In many systems, such blocks are fixed in size and are referred to as sections or pages. The addresses within individual pages all have the same most significant bit. Therefore, the memory address is a sequence of page numbers corresponding to the upper bits of the address and page offsets corresponding to the lower bits of the address.
    [32] In general, data structures are maintained in physical memory to translate from valid page numbers to actual page numbers. Often these data structures take the form of conversion tables, commonly referred to as segment tables and page tables. Segment tables are indexed by valid page addresses or numbers and generally have a number of entries corresponding to pages in the valid address space. Each entry is a mapping of a specific page number or valid page address to a virtual page address. The page table is indexed by virtual page address or number and generally has a number of entries corresponding to pages in the virtual address space. Each entry is a mapping of a specific page number or virtual page address to a real page address.
    [33] Effective-to-real address translation uses a processor unit (not shown) using a specialized translation cache or a specialized hardware cache (not shown) called a translation lookaside buffer (TLB). 10). TLB is a fast and compact static memory for storing the most commonly referenced entries from the page table. Generally it has a fixed number of entries. When processing a memory request, the computer first attempts to find a suitable address translation in the TLB. If no such address translation is found, the page table is automatically accessed to retrieve the appropriate translation.
    [34] Those skilled in the art will appreciate that the data processing system 8 may include additional components not shown, such as I / O adapters, interconnect bridges, nonvolatile storage, ports for networks or attached devices, and the like. Since such additional components are not necessary to understand the invention, it is not shown in FIG. 1 or described herein. However, it should be noted that the improvements provided by the present invention are applicable to data processing systems of any architecture and are by no means limited to the generalized MP structure shown in FIG.
    [35] 2, there is shown a memory mapping function performed by a memory management system for a virtual memory system of a data processing system 8, in accordance with a preferred embodiment of the present invention. The application address space represents an address space in which a plurality of processes operating in the processor unit 10 operate independently of each other. Three processes, Process 1 (P1), Process 2 (P2), and Process P3, are shown, each with its own logical address space. For each process, a page or block of addressable space is addressed by a valid address. As shown in FIG. 2, the valid addresses in the application address space of the page currently loaded in the physical address space are shown as P1-EA, P2-EA and P3-EA for each of the three executing processes. Each valid address is a 64-bit address that is translated by segment table translation 204. Segment table translation 204 is performed by a segment look-aside buffer (SLB) or segment look-aside register (SLR) in processor core 14. Each addressable space in the application address spaces P1, P2, and P3 is translated into an 80-bit virtual address in the virtual address space 206 by the SLB or SLR. Therefore, P1-EA, P2-EA and P3-EA are converted into P2-VA, P1-VA and P3-VA by segment table conversion, respectively. Using a translation lookaside buffer (TLB) in processor core 14, each virtual address space P1-VA, P2-VA and P3-VA can then be written to each 80-bit virtual address P1-VA, P2-VA and The P3-VA is converted to the real address space 210 by the page table transformation 208 so that P3-VA is converted to their 64-bit real addresses P1-RA, P2-RA and P3-RA representing the real addresses in system memory. Usually a physical address RA is a field that codes a physical page number into bits, e.g., the number of high bits "i", and a shift from the start of the physical page, bits, e.g., the number of low bits "j" It consists of two fields, which are fields to be coded with. The j square of two represents the size of the page, for example the number j equal to 12 represents the page size of 4 kilobytes. The i-square of two indicates the physical memory size in the number of pages, for example, the number i equal to 20 indicates one physical megapage or four gigabytes of physical memory.
    [36] As shown in FIG. 1, memory controllers 24, 34, and 44 physically map actual addresses to access requested pages of memory modules M1, M2, and M3. Thus, if an addressed page of the actual address space 210 is not found in the L1 caches 16, 18 and the L2 cache 20, memory access is required through the interconnect 12. When interconnect 12 detects a memory access request, each memory controller 24, 34, 44 examines the actual address space addressed by the memory access. The upper bits of the real address from the processor unit 10 are decoded by the memory controllers 24, 34 and 44, which identify the addressable real space of the corresponding memory modules M1, M2, M3 of each memory controller. do. Each memory controller 24, 34, and 44 responds to a memory access addressed to its corresponding memory module.
    [37] Thus, as shown in FIG. 2, physical mapping 212 is performed by memory controllers 24, 34, and 44. Physical mapping 212 translates the physical addresses for address pages P1-RA, P2-RA, and P3-RA and corresponds to the corresponding physical addresses P1 representing the physical addresses of the requested pages in corresponding memory modules M1, M2, and M3. Map to -PA, P2-PA and P3-RA, respectively. The physical address indicates a specific memory location of the memory module that stores the addressed information. For example, P2-PA specifies a particular row and column address for uniquely identifying the addressed page of memory module M2. This physical mapping mechanism is not visible to the operating system (OS), which does not deduce the location of the physical memory resources for a particular memory module M1, M2, M3 in the system memory 22, but all physical memory by physical address. Monitor resources.
    [38] Referring again to FIG. 1, a mapping engine 36 and a move engine are included in each processor unit 10. The mapping engine 36 and the movement engine 28 provide a virtualization function of the physical memory that allows for efficient reconstruction of the physical memory 22 according to a preferred embodiment. When physical memory 22 is reconfigured such that one of memory modules M1, M2, and M3 is added, removed, or replaced in the system, mobile engine 28 performs data transfer between memory modules of physical memory 22, The mapping engine 36 controls the actual addressing of the target memory modules of the memory modules M1, M2, M3 to allow addition, removal or replacement of specific memory modules. This memory management is efficiently performed at the hardware / firmware level, requiring less operating system resources to achieve physical memory reconfiguration. In operation, each mapping engine 36 provides a configurable allocation of real address space (especially high and real address bits) for the selected memory module being reconstructed, which effectively changes the base address of the memory device. .
    [39] 3 shows an embodiment in which the memory module is removed from the physical memory of the simplified diagram of the data processing system 8. As will be described, the processor's mobile engine works in conjunction with the associated mapping engine to bring the associated memory module off-line prior to physical removal of the memory module. In general, the mobile engine copies the contents of the memory module to be removed to the remaining memory modules of the physical memory. The real address of the memory module is then reallocated to the memory module receiving the copied contents.
    [40] In this example, memory module M2 is being removed from data processing system 8. As a first step, processor unit 10 informs the operating system that the available physical memory of the operating system is now reduced by one memory module. For example, if each memory module M1, M2, M3 is a 64 gigabyte (GB) memory device, the operating system is notified that the available physical memory of the operating system is now 128 GB. Thus, the operating system immediately begins swapping pages to reduce the amount of data stored. Processor unit 10 informs all mobile engines 28 and mapping engines 38 that memory module M2 is being removed from physical memory. The movement engine 28 immediately selects the remaining module (s) to be used to store the data contained in memory module M2.
    [41] Each mapping engine 36 in processor unit 10 has a " current " real address for the memory module being removed and a " new " real address for the memory module being removed (as used herein, The address points to a register 305 that stores the full physical address or portion thereof (e.g., high bit) needed to uniquely identify the associated memory module that stores the data addressed by the indexed block of memory. Include. Each processing unit 10 loads each register 305 as needed to perform a given memory reconfiguration.
    [42] As shown in FIG. 3, the mapping engine 36 includes a field 306 containing the FROM actual address of the memory module M2, and a corresponding memory module that holds the memory contents of the removed module, in this case memory module M3. It includes a register 305 having a field 308 containing the TO actual address. Register 305 includes a field 306 that shows the FROM real address of memory module M2 as RA2, and field 308 contains the TO real address, RA3, for memory module M2.
    [43] In the example shown in FIG. 3, the mobile engine 28 selects memory module M3 to receive data stored in memory module M2. Memory module M1 remains on-line and does not receive any data from memory module M2. After loading register 305, move engine 28 copies the contents of the memory address space at FROM physical address (RA2) into the memory address space at TO physical address (RA3). "Start. Thus, in order to copy each memory cell of memory module M2 into the memory address space at actual address RA3, the mobile engine 28 makes a memory access request to the memory controller 34 over the interconnect 12. Start copying the contents of memory module M2 to memory module M3. The mobile engine 28 thereby copies all the stored contents of the memory module M2 addressed by the real address RA2 to the memory module M3 addressed by the real address RA3, as shown by path 325. In another embodiment, the movement engine 28 copies a portion of the contents of memory module M2 to the remainder of memory module M3 and other memory modules of memory system 22 (eg, memory module M1).
    [44] During the process of moving memory storage contents, memory controllers 24, 34, and 44 continue to respond to memory access requests on interconnect 12. The mapping engine 36 provides the FROM physical address field 306 by providing a mapping to the physical addresses of the memory modules M2 and / or M3 to perform memory accesses directed to the current actual address space in accordance with a preferred embodiment. It allows each processor to generate memory requests such as "Read" and "Write" addressed in memory stored at the current physical address as indicated by. In the example of FIG. 3, memory module M2 continues to respond to a read addressed to real address RA2 as shown by path 327. According to a preferred embodiment, the mapping engine 36 sends a write request from the associated processor to the current actual address space, as indicated by the FROM and TO physical address fields 306 and 308, respectively; Map to a real address. Thus, as shown by path 329 of FIG. 3, the FROM actual address of memory module M2 (as shown in field 306) is RA2 and its (as shown in field 308). Since the TO real address is RA3, writing to the real address RA2 will be directed to the memory controllers 34 and 44. Since memory records into RA2 are stored in memory modules M2 and M3 continuously, it is ensured that the memory system is consistent during the move process.
    [45] After completing the data transfer from memory module M2 to memory module M3, move engine 28 updates register 305 by copying the TO real address into FROM real address field 306 or by resetting mapping engine 36. do. The memory controller 44 is then reprogrammed to respond to the actual address RA2 that was previously managed by the memory controller 34. Memory module M1 is now addressed by real address RA1 and memory module M3 is now addressed by real address RA2. The memory controller 44 now physically maps the physical address of the RA2 space directly to the memory module M3, thereby virtualizing the physical mapping from the addressable physical address space being used by the operating system to the virtual physical address space. Create
    [46] Referring to FIG. 4, a simplified block diagram of a data processing system 8 showing a memory module M2 being inserted into a physical memory 22 is shown. Each processor unit 10 tells each mobile engine 28 and mapping engine 36 that a memory module is being added to the physical memory 22 and associated with and controlled by the memory controller 34. Notify that it will be inserted into the controlled memory slot. In this regard, the current actual address space for the data processing system 8 consists of the physical memories of the memory modules M1 and M3 and is addressed by the actual address spaces RA1-RA2.
    [47] Each register 305 in each processor unit 10 is programmed with a respective current and new actual address in accordance with the preferred embodiment. The TO real address assigned to memory module M2 is programmed to a real address outside the current real address space of physical memory 22, in this case RA4. The FROM real address is the address to be allocated after the memory module being inserted has inserted and reprogrammed the real addressable space. Field 306 is programmed to FROM real address RA2 and field 308 is programmed to TO real address RA4. The memory controller associated with the memory module being inserted, in this case memory controller 34, is programmed to respond to the actual address RA4. As will be appreciated, the actual address selected for each field depends on the size of the memory module M2 being inserted and the size of the existing memory module M3. In this example, the sizes are assumed to be the same size. If they have different sizes, the actual address for memory module M3 will be chosen to fall on the memory boundary of memory module M2 to provide contiguous real memory space.
    [48] After memory module M2 is physically inserted into physical memory 22 and loads register 305, mobile engine 28 reads the contents of the memory address space at FROM physical address RA2 from TO physical address RA4. Initiate a "move process" to copy into the memory address space. Thus, the mobile engine 28 sends a memory access request on the interconnect 12 to the memory controller 44 to copy each memory cell of the memory module M3 into the memory address space of the actual address RA4, thereby causing the memory module M3 to be lost. Start copying the contents to memory module M2. Memory controller 44 receives a write from each memory cell of memory module M3 and maps it to the physical address space of memory module M2. This is illustrated in FIG. 4 by path 425 showing copying the memory cell at actual address RA2 to the memory cell at real address RA4.
    [49] During the migration process, the mapping engine 36 is programmed to respond to memory access by the processor unit 10 addressed to the FROM real address programmed into the register 305 in the field 306. As shown in FIG. 4, read memory access from the processor unit 10 indicated by the real address RA2 is subsequently serviced by the memory controller 44, which is programmed to respond to the real address space RA2. The write memory access from processor unit 10 indicated by real address RA2 is a memory controller (in this case memory controllers 34 and 44) that responds to memory accesses to the FROM and TO real addresses of register 305, respectively. The mapping engine 36 will issue a write memory request to the furnace. These memory controllers will write the received data to the combined memory module by physically mapping to corresponding row and column physical addresses. As shown in Fig. 4, a write request from the processor unit 10 to the actual address RA2 is shown by the path 429, which requests the memory while allowing each memory module M2 and M3 to be updated by the recorded data. Received by the controllers 34 and 44. As will be appreciated, this mechanism allows for memory coherence during the migration process.
    [50] After the memory module move process is complete, the move engine 28 instructs the memory controller 34 to respond to memory access from the interconnect 12 at the FROM physical address of the field 306 and the memory controller 44 Instruct to respond to a memory access from interconnect 12 at another real address in the reconstructed real memory space. In this example, memory controller 44 is reprogrammed to real address RA3 to provide a contiguous real addressable memory RA1-RA3. The operating system is then notified that the actual address space of the operating system has been increased by the same amount as the addressable space of the memory module M2. The operating system will then begin storing and accessing memory pages over the actual address space RA1-RA3 of the memory modules M1, M2, and M3.
    [51] As will be appreciated, there is a case where the actual address space does not need to be reconstructed to match the memory boundary of the memory in which the memory module being inserted is present. Therefore, in another embodiment, the memory move process is not performed and the mapping engine 36 immediately programs the memory controller associated with the inserted memory module to respond to the TO actual address associated with the newly added real address space. For example, if memory module M2 is being added to physical memory 22 as shown in FIG. 4, each of fields 306 and 308 are programmed to actual address RA3. In this case, data stored in the memory module M3 is not copied to the memory module M2 but remains in the memory module M3. After memory module M2 has been added to a memory slot in physical memory 22, the physical address space has been increased by the same amount as the memory storage space of memory module M2 and memory controller 34 immediately responds to memory accesses to physical address RA3. Notify the operating system that it is starting.
    [52] In the case of replacing the memory module of the physical memory 22, the memory module is removed from the physical memory 22 according to the process described with reference to FIG. 3, and then the new memory module is removed from the process described with respect to FIG. Thus it is reinserted into physical memory. Referring again to FIG. 1, the mapping engine 56 in the input / output connector 52 operates in the same manner as the mapping engine 36. The input / output connector 52 operates in a similar manner as the processor unit 10 when performing the memory access operation directly to the memory module being reconfigured according to the preferred embodiment. As will be appreciated, the system may have additional input / output connectors identical to the input / output connectors 52 connected to the interconnects 12. When various input / output devices, such as disk drives and video monitors, are added and removed from the PCI bus 58 (or other similar attached bus), the mapping engine 56 may physically allow the virtualization of physical addresses to such input / output devices. Removal and addition of memory modules of memory 22 will operate with mobile engine 28 in the same manner as above.
    [53] As will be appreciated, the preferred embodiment allows memory modules to be inserted, removed or replaced in physical memory 22 without the operating system instructing and reconfiguring the physical memory to achieve physical memory changes. In the preferred embodiment, the movement engine 28 and the mapping engine 36 work together to transparently reconfigure the physical memory to achieve adding, removing or replacing specific memory modules of the physical memory. Each mapping engine allows the movement and mapping engine to virtualize the physical address for the memory module being reconstructed, and stores current and new physical addresses that reconstruct and process stored data in real time using hardware rather than software. do.
    [54] While the invention has been shown and described with reference to preferred embodiments, those skilled in the art will understand that various modifications may be made in form and detail without departing from the spirit and scope of the invention.
    [55] According to the present invention, memory modules can be inserted, removed or replaced in physical memory without the operating system instructing and reconfiguring the physical memory to achieve physical memory changes. In addition, the movement engine and the mapping engine may work together to transparently reconfigure physical memory to achieve adding, removing or replacing specific memory modules of the physical memory. Each mapping engine allows the movement and mapping engine to virtualize the physical address for the memory module being reconstructed and store current and new physical addresses that reconstruct and process stored data in real time using hardware rather than software. Can be.
    权利要求:
    Claims (17)
    [1" claim-type="Currently amended] A computing system coupled to physical memory including a plurality of memory modules to store data as a plurality of memory blocks, each memory block comprising a contiguous byte of physical memory, the computing system being further coupled to at least one memory controller; Wherein each memory controller of the at least one memory controller includes one or more memory modules of the plurality of memory modules connected to it, each memory controller of the at least one memory controller being one of the memory modules connected to it. In response to a memory access by writing and reading a memory block stored in the above;
    A processor device for generating a memory access including a physical address associated with a memory location of the physical memory system for reading and writing data to a memory location of the physical memory system;
    A first field for storing a FROM physical address corresponding to a first memory module among the plurality of connected memory modules, and a second field for storing a TO physical address corresponding to a second memory module among the plurality of connected memory modules; A register in the processor device-a first memory controller coupled to the first memory module is programmed to respond to a memory request addressed to the FROM physical address, and a second memory controller coupled to the second memory module is assigned to the TO physical address. Programmed to respond to addressed memory requests-;
    In response to a notification that configurations of the first memory module and the second memory module are being modified, the plurality of memory blocks are allocated from the first memory module to the second memory module based on the FROM real address and the TO real address. A mobile engine in the processor device for copying to the processor; And
    The processor device is addressed to the physical address stored in one of the first field or the second field during a time period during which the mobile engine is copying the plurality of memory blocks from the first memory module to the second memory module. In response to generating a write memory request, generate a write memory request addressed to the FROM real address and the TO real address, and wherein the mobile engine copies the plurality of memory blocks from the first memory module to the second memory module. A mapping engine in the processor device reprogramming the second memory controller to respond to a memory request addressed to the FROM real address after the time interval being performed
    Computing system comprising a.
    [2" claim-type="Currently amended] The write memory request of claim 1, wherein the processor device is further configured to: address the FROM physical address during the time period during which the mobile engine is copying the plurality of memory blocks from the first memory module to the first memory module. And in response, the mapping engine issues the write memory request addressed to the FROM real address and the TO real address.
    [3" claim-type="Currently amended] 2. The method of claim 1, wherein after the time period during which the mobile engine is copying the plurality of memory blocks from the first memory module to the second memory module, the mapping engine causes the second memory controller to move to the FROM real address. And the first memory module is removed from the physical memory system after enabling to respond to an addressed memory access.
    [4" claim-type="Currently amended] 4. The method of claim 3, wherein the FROM real address is current addressable of the physical memory system prior to the time period during which the mobile engine is copying the plurality of memory blocks from the first memory module to the second memory module. Computing system in space.
    [5" claim-type="Currently amended] The computing system of claim 1, wherein the second memory module is inserted into the physical memory system before the movement engine copies the plurality of memory blocks from the first memory module to the second memory module.
    [6" claim-type="Currently amended] 6. The method of claim 5, wherein the FROM real address is current addressable of the physical memory system prior to the time period during which the mobile engine is copying the plurality of memory blocks from the first memory module to the second memory module. Computing systems out of space.
    [7" claim-type="Currently amended] A processor device for creating a memory access including a physical address associated with a memory location of the physical memory system to read and write data to a memory location of a physical memory system, the physical memory system including a plurality of memory controllers; Wherein each memory controller is responsive to a memory access required by the processor device by writing and reading a memory block stored in one or more memory modules connected thereto;
    Setting a register in the processor device to indicate a FROM real address and a TO real address corresponding to the first and second memory modules, respectively, wherein the first and second memory modules are coupled to first and second memory controllers, respectively. Is-;
    Copying the plurality of memory blocks from the first memory module to the second memory module based on the FROM real address and the TO real address;
    Before completing the copying step, the processor device is addressed to the FROM real address and the TO real address in response to issuing a write memory request addressed to the real address stored in either the first field or the second field. Generating a write memory request; And
    After the copying step is completed, configuring the first and second memory controllers to respond only to memory accesses addressed to new physical addresses.
    Data processing method comprising a.
    [8" claim-type="Currently amended] 8. The data processing of claim 7, wherein, during the copying step, a write memory request addressed to the FROM real address and the TO real address is generated in response to the processor device generating a write memory request addressed to a current real address. Way.
    [9" claim-type="Currently amended] 8. The method of claim 7, further comprising the step of removing the first memory module from the physical memory system subsequent to the configuring step, wherein the FROM physical address is within current addressable space of the physical memory system. Processing method.
    [10" claim-type="Currently amended] 8. The method of claim 7, further comprising inserting the first memory module into the memory system prior to the copying, wherein the TO physical address is outside the current addressable space of the physical memory system. .
    [11" claim-type="Currently amended] 8. The method of claim 7, further comprising notifying the processor that a configuration of the plurality of memory modules is being modified, wherein the setting step is performed in response to the notification.
    [12" claim-type="Currently amended] A physical memory system comprising a plurality of memory modules for storing data as a plurality of memory blocks, each memory block comprising consecutive bytes of physical memory;
    A plurality of memory controllers-each memory controller of the plurality of memory controllers comprises at least one memory module of the plurality of memory modules connected to it, each memory controller of the plurality of memory controllers being at least one memory module connected to it Respond to memory accesses by writing and reading memory blocks stored in the memory; And
    A plurality of processor devices for generating memory accesses including actual addresses associated with memory locations of the physical memory system for reading and writing data to memory locations of the physical memory system
    Including, wherein each processor device of the plurality of processor devices,
    A first field for storing a FROM physical address corresponding to a first memory module among the plurality of connected memory modules, and a second field for storing a TO physical address corresponding to a second memory module among the plurality of connected memory modules; Wherein the first memory controller coupled to the first memory module is programmed to respond to a memory request addressed to the FROM physical address, and the second memory controller coupled to the second memory module is a memory request addressed to the TO address. Programmed to respond to;
    In response to a notification that configurations of the first and second memory modules are being modified, copying the plurality of memory blocks from the first memory module to the second memory module based on the FROM real address and the TO real address. Moving engine; And
    The processor device addresses the physical address stored in one of the first field or the second field during the time period during which the mobile engine is copying the plurality of memory blocks from the first memory module to the second memory module. In response to requesting a designated write memory request, generating a write memory request addressed to the FROM real address and the TO real address, wherein the mobile engine transfers the plurality of memory blocks from the first memory module to the second memory module. A mapping engine reprogramming said second memory controller to respond to a memory request addressed to said FROM physical address after said time period of copying
    Data processing system comprising a.
    [13" claim-type="Currently amended] 13. The processor device of claim 12, wherein the processor device issues a write memory request addressed to the FROM physical address during the time period during which the mobile engine is copying the plurality of memory blocks from the first memory module to the second memory module. In response to the request, the mapping engine generating the write memory request addressed to the FROM real address and the TO real address.
    [14" claim-type="Currently amended] 13. The method of claim 12, wherein after the time period during which the mobile engine is copying the plurality of memory blocks from the first memory module to the second memory module, the mapping engine causes the second memory controller to move to the TO physical address. And wherein said first memory module is removed from said physical memory system after enabling to respond to an addressed memory access.
    [15" claim-type="Currently amended] 15. The method of claim 14, wherein the FROM real address is current addressable of the physical memory system before the time period during which the mobile engine is copying the plurality of memory blocks from the first memory module to the second memory module. Data processing system in space.
    [16" claim-type="Currently amended] The data processing system of claim 12, wherein the second memory module is inserted into the physical memory system before the mobile engine copies the plurality of memory blocks from the first memory module to the second memory module.
    [17" claim-type="Currently amended] 17. The apparatus of claim 16, wherein the FROM physical address is current addressable of the physical memory system before the time period during which the mobile engine is copying the plurality of memory blocks from the first memory module to the second memory module. Data processing system out of space.
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    同族专利:
    公开号 | 公开日
    KR100515229B1|2005-09-16|
    CN1227594C|2005-11-16|
    CN1489059A|2004-04-14|
    US20040073743A1|2004-04-15|
    US6904490B2|2005-06-07|
    TWI236592B|2005-07-21|
    TW200413917A|2004-08-01|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-10-10|Priority to US10/268,743
    2002-10-10|Priority to US10/268,743
    2003-09-05|Application filed by 인터내셔널 비지네스 머신즈 코포레이션
    2004-04-17|Publication of KR20040032745A
    2005-09-16|Application granted
    2005-09-16|Publication of KR100515229B1
    优先权:
    申请号 | 申请日 | 专利标题
    US10/268,743|US6904490B2|2002-10-10|2002-10-10|Method and system of managing virtualized physical memory in a multi-processor system|
    US10/268,743|2002-10-10|
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